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preliminary roboclock ? CY7B9945V high speed multi-phase pll clock buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07336 rev. *j revised march 15, 2011 features 500 ps max total timing budget (ttb?) window 24 mhz ?200 mhz input and output operation low output-output skew <200 ps 10 + 1 lvttl outputs driving 50 terminated lines dedicated feedback output phase adjustments in 625ps/1300 ps steps up to +10.4 ns 3.3 v lvttl/lvpecl, fault to lerant, and hot insertable reference inputs multiply or divide ratios of 1 through 6, 8, 10, and 12 individual output bank disable output high impedance option for testing purposes integrated phase locked loop (pll) with lock indicator low cycle-cycle jitter (<100 ps peak-peak) 3.3 v operation industrial temperature range: ?40 c to +85 c 52-pin 1.4 mm tqfp package functional description the CY7B9945V high speed multi-phase pll clock buffer offers user selectable control over syste m clock functions. this multiple output clock driver provides t he system integrator with functions necessary to optimize the timing of high performance computer and communication systems. the device features a guaranteed maximum ttb window speci- fying all occurrences of output clocks. this includes the input reference clock across variations in output frequency, supply voltage, operating te mperature, input edge rate, and process. ten configurable outputs each drive terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews at lvttl levels. the outputs are arranged in two banks of four and six outputs. these banks enable a divide function of 1 to 12, with phase adjustments in 625 ps?1300 ps increments up to 10.4 ns. the dedicated feedback output enables divide-by functio nality from 1 to 12 and limited phase adjustments. however, if needed, any one of the ten outputs can be connected to the feedback input as well as driving other inputs. selectable reference input is a fault tolerant feature that enables smooth change over to a secondary clock source when the primary clock source is not in operation. the reference inputs and feedback inputs are configurable to accommodate both lvttl or differential (lvpecl) inputs. the completely integrated pll reduces jitter and simplifies board layout. pll fbk qf 2q0 2q1 2q2 2q3 divide and phase select dis2 lock fs 1q0 1q1 1q2 1q3 divide and phase select 3 3 2f0 2f1 3 3 2ds0 2ds1 divide and phase select 3 fbf0 3 3 fbds0 fbds1 dis1 refa- refa+ refb- refb+ 3 3 3 1f0 1f1 3 3 1f2 1f3 3 3 1ds0 1ds1 2q4 2q5 refsel mode logic block diagram [+] feedback
preliminary roboclock ? CY7B9945V document number: 38-07336 rev. *j page 2 of 15 contents pinouts .............................................................................. 3 pin definitions .................................................................. 3 block diagram description .............................................. 4 time unit definition .......................................................... 4 divide and phase select matrix ....................................... 4 output disable description ............................................. 6 lock detect output description ................................... 7 factory test mode description ................................... 7 safe operating zone ................................................... 7 absolute maximum conditions ....................................... 8 operating range ............................................................... 8 electrical characteristics over the operating range ... 8 capacitance ...................................................................... 9 ordering information ...................................................... 11 package diagram ............................................................ 12 acronyms ....................................................................... 13 document conventions ................................................. 13 units of measure ...................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc solutions ......................................................... 15 [+] feedback
preliminary roboclock ? CY7B9945V document number: 38-07336 rev. *j page 3 of 15 pinouts figure 1. pin configuration CY7B9945V 2f1 2f0 2ds1 gnd 2q0 vccn 2q1 2q2 vccn 2q3 gnd 1ds1 2ds0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1ds0 gnd vccq 1f3 1f1 dis1 2q4 vccn 2q5 gnd gnd mode dis2 refa- refsel refb- refb+ 1f2 fs gnd 1q2 vccn 1q3 fbf0 1f0 vccq lock fbds1 fbds0 gnd 1q0 vccn 1q1 vccn qf gnd fbk vccq refa+ pin definitions pin name io type description 34 fs input three level input frequency select . this input must be set according to the nominal frequency (f nom ). see ta b l e 1 . 40,39, 36,37 refa+, refa- refb+, refb- input lvttl/ lvdiff reference inputs . these inputs can operate as differential pecl or single-ended ttl reference inputs to the pll. when operating as a single-ended lvttl input, the complementary input is left open. 38 refsel input lvttl reference select input . the refsel input contro ls the configuration of reference input when low, it uses the re fa pair as the reference input. when high, it uses the refb pair as the reference input. this input has an internal pull down. 42 fbk input lvttl feedback input clock . the pll operates such that the rising edges of the reference and feedback signals are aligned in phase and frequency. this pin provides the clock output qf feedback to the phase detector. 28,18, 35,17, 2, 1 1f[0:3], 2f[0:1] input three level input output phase function select . each pair determines the phase of the respective bank of outputs. see table 3 . 19,26 dis[1:2] input lvttl output disable . each input controls the state of the respective output bank. when high, the output bank is disabled to hold-off or high-z state; the disable state is determined by mode. when low, outputs 1q[0:3] and 2q[0:5] are enabled. see ta b l e 5 . 14,12, 13,3 [1:2]ds[0: 1] input three level input output divider function select . each pair determines the divider ratio of the respective bank of outputs. see table 4 . 29 fbf0 input three level input feedback output phase function select . this input determines the phase of the qf output. see ta b l e 3 . 50,51 fbds[0:1] input three level input feedback output divider function select . this input determines the divider ratio of the qf output. see ta b l e 4 . 48,46, 32,30, 5,7,8,10, 20,22 1q[0:3], 2q[0:5] output lvttl clock outputs with adjustable phases and f nom divide ratios . the output frequencies and phases are determined by [1:2]ds[0:1], and 1f[0:3] and 2f[0:1], respectively. see table 3 and table 4 . 44 qf output lvttl feedback clock output . this output is connected to the fbk input. the output frequency and phase are determined by fbds[0:1] and fbf0, respectively. see ta b l e 3 and ta b l e 4 . 52 lock output lvttl pll lock indicator . when high, this output indicate s that the internal pll is locked to the reference signal. when low, it indicates that the pll is attempting to acquire lock [+] feedback
preliminary roboclock ? CY7B9945V document number: 38-07336 rev. *j page 4 of 15 block diagram description the pll adjusts the phase and the frequency of its output signal to minimize the delay between the reference (refa/b+, refa/b-) and the feedback (fb) input signals. the CY7B9945V has a flexible ref input scheme. these inputs enable the use of either differential lvpecl or single ended lvttl inputs. to configure as single ended lvttl inputs, leave the complementary pin open (internally pulled to 1.5 v), then the other input pin is used as a lvttl input. the ref inputs are also tolerant to hot insertion. the ref inputs are changed dynamically. when changing from one reference input to the other reference input of the same frequency, the pll is optimized to ensure that the clock outputs period is not less than the calculated system budget (tmin = tref (nominal refe rence period) ? tccj (cycle-cycle jitter) ? tpdev (max. period deviation)) while reacquiring lock. the fs control pin setting determines the nominal operational frequency range of the divide by one output (fnom) of the device. fnom is directly related to the vco frequency. the fs setting for the device is shown in ta b l e 1 . for CY7B9945V, the upper fnom range extends from 96 mhz to 200 mhz. time unit definition selectable skew is in discret e increments of time unit (t u ). the value of a t u is determined by the fs setting and the maximum nominal output frequency. the equation determines the t u value as follows: t u = 1/(f nom *n). n is a multiplication factor that is determined by the fs setting. f nom is nominal frequency of the device. n is defined in table 2 . divide and phase select matrix the divide select matrix is comprised of three independent banks: two of clock outputs and one for feedback. the phase select matrix, enables independent phase adjustments on 1q[0:1], 1q[2:3] and 2q[0:5]. the frequency of 1q[0:3] is controlled by 1ds[0:1] while the frequency of 2q[0:5] is controlled by 2ds[0:1]. the phas e of 1q[0:1] is controlled by 1f[0:1], that of 1q[2:3] is contro lled by 1f[2:3] and that of 2q[0:5] is controlled by 2f[0:1]. the high fanout feedback output bu ffer (qf) connects to the feedback input (fbk).this feedback output has one phase function select input (fbf0) and two divider function selects fbds[0:1]. the phase capabilities that ar e chosen by the phase function select pins are shown in ta b l e 3 . the divide capabilities for each bank are shown in table 4 . 25 mode input three level input this pin determines the clock outputs? disable state . when this input is high, the clock outputs disables to hi gh impedance state (high-z). when this input is low, the clock outputs disables to hold-off mode. when in mid, the device enters factory test mode. 6,9,21, 31, 45, 47 vccn pwr power supply for the output buffers 16,27, 41 vccq pwr power supply for the internal circuitry 4,11,15, 23,24, 33,43,49 gnd pwr device ground pin definitions pin name io type description table 1. frequency range select fs [1] f nom (mhz) min max low 24 52 mid 48 100 high 96 200 table 2. n factor determination fs CY7B9945V n f nom (mhz) at which t u = 1.0 ns low 32 31.25 mid 16 62.5 high 8 125 table 3. output phase select control signal output phase function 1f1 1f0 1q[0:1] 1f3 1f2 1q[2:3] 2f1 2f0 2q[0:5] fbf0 qf low low ?4t u ?4t u ?8t u ?4t u low mid ?3t u ?3t u ?7t u n/a low high ?2t u ?2t u ?6t u n/a mid low ?1t u ?1t u bk1q[0:1] [2] n/a mid mid 0t u 0t u 0t u 0t u mid high +1t u +1t u bk1q[2:3] [2] n/a high low +2t u +2t u +6t u n/a high mid +3t u +3t u +7t u n/a high high +4t u +4t u +8t u +4t u table 4. output divider select control signal output divider function [1:2]ds1 and fbds1 [1:2]ds0 and fbds0 bank1 bank2 feedback low low / 1 / 1 / 1 low mid / 2 / 2 / 2 low high / 3 / 3 / 3 [+] feedback
preliminary roboclock ? CY7B9945V document number: 38-07336 rev. *j page 5 of 15 figure 2 shows the timing relationship of programmable skew outputs. all times are measured with respect to ref with the output used for feedback programmed with 0t u skew. the pll naturally aligns the rising edge of the fb input and ref input. if the output used for feedback is programmed to another skew position, then the whole t u matrix shifts with respect to ref. for example, if the output used for feedback is programmed to shift ?4tu, then the whole matrix is shifted forward in time by 4tu. thus an output programmed with 4t u of skew gets effectively be skewed 8t u with respect to ref. figure 2. typical outputs with fb connected to a zero-skew output [3] mid low / 4 / 4 / 4 mid mid / 5 / 5 / 5 mid high / 6 / 6 / 6 high low / 8 / 8 / 8 high mid / 10 / 10 / 10 high high / 12 / 12 / 12 table 4. output divider select control signal output divider function [1:2]ds1 and fbds1 [1:2]ds0 and fbds0 bank1 bank2 feedback t 0 ? 6t u t 0 ? 5t u t 0 ? 4t u t 0 ? 3t u t 0 ? 2t u t 0 ? 1t u t 0 t 0 +1t u t 0 t 0 t 0 t 0 t 0 +2t u +3t u +4t u +5t u +6t u fbinput refinput ?8t u ?7t u ?6t u ?4t u ?3t u ?2t u ?1t u 0t u +1t u +2t u +3t u ll lm lh (n/a) (n/a) (n/a) (n/a) mm (n/a) (n/a) (n/a) (n/a) hl (n/a) ll lm lh ml mh mm hm hh (n/a) (n/a) (n/a) +4t u +6t u +7t u +8t u t 0 ? 8t u t 0 ? 7t u t 0 +7t u t 0 +8t u hm hh hl (n/a) (n/a) 2f[1:0] 1f[3:2] 1f[1:0] [+] feedback
preliminary roboclock ? CY7B9945V document number: 38-07336 rev. *j page 6 of 15 output disable description the output of each output bank c an be independently put into a hold off or high impedance st ate. the combination of the mode and dis[1:2] inputs determ ines the clock outputs? state for each bank. when the dis[1:2] is low, the outputs of the corresponding banks are enabled. when dis[1:2] is high, the outputs for that bank are disabled to a high impedance (hi-z) or hold off state. ta b l e 5 defines the disabled outputs functions. the hold off state is a power saving feature. an output bank is disabled to the hold off state in a maximum of six output clock cycles from the time th e disable input is high. when disabled to the hold off state, outputs are driven to a logic low state on their falling edges. this makes certain that the output clocks are st opped without a glitch . when a bank of outputs is disabled to hi-z stat e, the respective bank of outputs go high-z immediately. table 5. dis[1:2] functionality mode dis[1:2] 1q[0:3], 2q[0:5] high/low low enabled high high hi-z low high hold-off mid x factory test notes 1. fb connected to an output selected for ?zero? skew (i.e., fbf0 = mid or xf[1:0] = mid). 2. the level set on fs is determined by the ?nominal? operating frequency (f nom ) of the v co and phase generator. f nom always appears on an output when the output is operating in the undivided mode. the ref and fb are at f nom when the output connected to fb is undivided. 3. bk1q denotes following the skew setting of indicated bank1 outputs. 4. these inputs are normally wired to v cc , gnd, or left unconnected (actual threshold voltages vary as a percentage of v cc ). internal termination resistors hold the unconnected inputs at v cc /2. if these inputs are switched, the function and timing of the outputs may glitch and the pll may require an additional t lock time before all data sheet limits are achieved. 5. this is for non-three level inputs. [+] feedback
preliminary roboclock ? CY7B9945V document number: 38-07336 rev. *j page 7 of 15 lock detect output description the lock detect output indicates the lock condition of the integrated pll. lock detection is accomplished by comparing the phase difference between the reference and feedback inputs. phase error is declared when the phase difference between the two inputs is grea ter than the specified device propagation delay limit t pd . when in the locked state, after four or more consecutive feedback clock cycles with phase errors, the lock output is forced low to indicate out-of-lock state. when in the out-of-lock state, 32 consecutive phase errorless feedback clock cycles are required to enable the lock output to indicate lock condition (lock = high). if the feedback clock is removed after lock has gone high, a ?watchdog? circuit is implement ed to indicate the out-of-lock condition after a time-out period by deasserting lock low. this time out period is based upon a divided down reference clock. this assumes that there is acti vity on the selected ref input. if there is no activity on the selected ref input then the lock detect pin does not accurately reflect the state of the internal pll. factory test mode description the device enters factory test mode when the mode is driven to mid. in factory test mode, th e device operates with its internal pll disconnected; input level supplied to the reference input is used in place of the pll output. in test mode the fb input is tied low. all functions of the device remain operational in factory test mode except the internal pll and output bank disables. the mode input is desi gned as a static input. dynam- ically toggling this input from low to high temporarily causes the device to go into factory test mode (when passing through the mid state). when in the test mode, the device is reset to a deterministic state by driving the dis2 input high. doing so disables all outputs and, after the selected reference clock pin has five positive transitions, all internal finite state machines (fsm) are set at a deterministic state. the states depend on the configurations of the divide, skew and frequency selection. all clock outputs stay in high-z mode and all fsms stay in the deterministic state until dis2 is deasserted. this causes the device to reenter factory test mode. safe operating zone figure 3 shows the operating condition of the device not exceeding its allowable maximum junction temperature of 150c. figure 3 shows the maximum numbe r of outputs that can operate at 185 mhz (with 25 pf load and no air flow) or 200 mhz (with 10-pf load and no air flow) at various ambient tempera- tures. at the limit line, a ll other outputs ar e configured to divide-by-two (i.e., operating at 92.5 mhz) or lower frequencies. the device operates below maximum allowable junction temper- ature of 150c when its conf iguration (with the specified constraints) falls within the shaded region (safe operating zone). figure 3 shows that at 85c, the maximum number of outputs that can operate at 200 mhz is 6. figure 3. typical safe operating zone typical safe operating zone (25-pf load, 0-m/s air flow) 50 55 60 65 70 75 80 85 90 95 100 246810 number of outputs at 185 mhz ambient temperature (c) safe operating zone [+] feedback
preliminary roboclock ? CY7B9945V document number: 38-07336 rev. *j page 8 of 15 absolute maximum conditions exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .... ............ ............... ?40 c to +125 c ambient temperature with power applied ..... ............ ........... ....... ?40 c to +125 c supply voltage to ground potentia l..............?0.5 v to +4.6 v dc input voltage ................................... ?0.3 v to v cc +0.5 v output current into outputs (low)............................. 40 ma static discharge voltage.......................................... > 1100 v (mil-std-883, method 3015) latch-up current.................................................. > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 3.3 v 10% industrial ?40 c to +85 c 3.3 v 10% electrical characteristics over the operating range description test conditions min max unit lvttl high voltage (qf, 1q[0:3], 2q[0:5]) v cc = min, i oh = ?30 ma 2.4 ?v lock i oh = ?2 ma, v cc = min 2.4 ? v lvttl low voltage (qf, 1q[0:3], 2q[0:5]) v cc = min, i ol = 30 ma ? 0.5 v lock i ol = 2 ma, v cc = min ? 0.5 v high impedance state leakage current ?100 100 a lvttl input high min < v cc < max 2.0 v cc + 0.3 v lvttl input low min. < v cc < max. ?0.3 0.8 v lvttl v in >v cc v cc = gnd, v in = 3.63 v ? 100 a lvttl input high current v cc = max, v in = v cc ? 500 a lvttl input low current v cc = max, v in = gnd ?500 ? a three level input high [4] min < v cc < max 0.87 * v cc ?v three level input mid [4] min < v cc < max 0.47 * v cc 0.53 * v cc v three level input low [4] min < v cc < max ? 0.13 * v cc v three level input high current fs[0:2],if[0:3],fbds[0:1] v in = v cc ? 200 a 2f[0:1],[1:2]ds[0:1],fbfo ? 400 a three level input mid current fs[0:2],if[0:3],fbds[0:1] v in = v cc /2 ?50 50 a 2f[0:1],[1:2]ds[0:1],fbfo ?100 100 a three level input low current fs[0:2],if[0:3],fbds[0:1] v in = gnd ?200 ? a 2f[0:1],[1:2]ds[0:1],fbfo ?400 ? a input differential voltage 400 v cc mv highest input high voltage 1.0 v cc v lowest input low voltage gnd v cc ? 0.4 v common mode range (crossing voltage) 0.8 v cc ? 0.2 v internal operating current CY7B9945V v cc = max, f max [5] ? 250 ma output current dissipation/pair [4] CY7B9945V v cc = max, c load = 25 pf, r load = 50 at v cc /2, f max ?40 ma [+] feedback
preliminary roboclock ? CY7B9945V document number: 38-07336 rev. *j page 9 of 15 capacitance parameter description test conditions min max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3 v ? 5 pf switching characteristics over the operating range [5, 7, 8, 9, 10] parameter description CY7B9945V-2 CY7B9945V-5 unit min max min max f in clock input frequency 24 200 24 200 mhz f out clock output frequency 24 200 24 200 mhz t skewpr matched pair skew [12, 13] ,1q[0:1],1q[2:3],2q[0:1],2q[2:3],2q[4:5] ? 200 ? 200 ps t skewbnk intrabank skew [12, 13] ?250?250ps t skew0 output-output skew (same frequency and phas e, rise to rise, fall to fall) [12, 13] ?250?550ps t skew1 output-output skew (same frequen cy and phase, other banks at different frequency, rise to rise, fall to fall) [12, 13] ?250?650ps t skew2 output-output skew (all output configurations outside of t skew0 and t skew1 ) [10, 11] ?500?800ps t ccj1-3 cycle-to-cycle jitter (divide by 1 output fr equency, fb = divide by 1, 2, 3) ? 150 ? 150 ps peak- peak t ccj4-12 cycle-to-cycle jitter (divide by 1 output frequency, fb = divide by 4, 5, 6, 8, 10, 12) ?100?100ps peak- peak t pd propagation delay, ref to fb rise ?250 250 ?500 500 ps ttb total timing budget window (same frequency and phase) [14, 15] ?500?700ps t pddelta propagation delay difference between two devices [16] ?200?200ps t refpwh ref input (pulse width high) [5] 2.0 ? 2.0 ? ns t refpwl ref input (pulse width low) [5] 2.0 ? 2.0 ? ns t r /t f output rise/fall time [17] 0.15 2.0 0.15 2.0 ns t lock pll lock time from power up ? 10 ? 10 ms t relock1 pll relock time (from same frequency, different phase) with stable power supply ?500?500 s t relock2 pll re-lock time (from different frequency, different phase) with stable power supply [16] ?1000?1000 s t odcv output duty cycle deviation from 50% [11] ?1.0 1.0 ?1.0 1.0 ns t pwh output high time deviation from 50% [19] ?1.5?1.5ns t pwl output low time deviation from 50% [19] ?2.0?2.0ns t pdev period deviation when changing from reference to reference [20] ? 0.025 ? 0.025 ui t oaz dis[1:2] high to output high-impedance from active [12, 21] 1.0101.010 ns t oza dis[1:2] low to output active fr om output is high impedance [21] 0.5140.514 ns notes 6. assumes 25 pf maximum load capacitance up to 185 mhz. at 200 mhz the maximum load is 10 pf. 7. both outputs of pair must be terminated, even if only one is being used. 8. each package must be properly decoupled. 9. ac parameters are measured at 1.5 v, unless otherwise indicated. 10. test load c l = 25 pf, terminated to v cc /2 with 50 up to185 mhz and 10 pf load to 200 mhz. 11. skew is defined as the time between the earliest and the late st output transition among all outputs for which the same phase delay has been selected when all outputs are loaded with 25 pf and properly terminate d up to 185 mhz. at 200 mhz the max load is 10 pf. 12. tested initially and after any design or pr ocess changes that affect these parameters. 13. ttb is the window between the earliest and the latest output cl ocks with respect to the input reference clock across variati ons in output frequency, supply voltage, operating temperature, input clock edge rate, and process. the me asurements are taken with the ac test load specified and inclu de output-output skew, cycle-cycle jitter, and dynamic phase error. ttb is equal to or smaller than the maximum specified value at a given output freq uency. [+] feedback
preliminary roboclock ? CY7B9945V document number: 38-07336 rev. *j page 10 of 15 figure 4. ac test loads and waveforms figure 5. ac timing diagram . 2.0 v 0.8 v 3.3 v gnd 2.0 v 0.8 v 3.3 v output (a) lvttl ac test load < 1ns < 1 ns (b) ttl input test waveform r1 r2 c l r1 = 910 r2 = 910 c l <30pf (includes fixture and probe capacitance) r1 = 100 r2 = 100 c l < 25 pf to 185 mhz for lock output only for all other outputs or 10 pf at 200 mhz t pwl t pwh ref fb q t refpwh t refpwl t pd t ccj1-3,4-12 [1:2]q[0,2] t skewpr [1:2]q[0:3] [1:2]q[0:3] t skewbnk t skewpr t skewbnk q other q t skew0,1 t skew0,1 2.0 v 0.8 v t odcv t odcv ref to device 1 and 2 fb device1 fb device2 t pd t pdelta t pdelta [1:2]q[1,3] notes 14. guaranteed by statistical correlation. tested initially and afte r any design or process changes that affects these parameter s. 15. rise and fall times are measured between 2.0 v and 0.8 v. 16. f nom must be within the frequency range defined by the same fs state. 17. t pwh is measured at 2.0 v. t pwl is measured at 0.8 v. 18. ui = unit interval. examples: 1 ui is a full period. 0.1ui is 10% of period. 19. measured at 0.5 v deviation from starting voltage. 20. for t oza minimum, c l = 0 pf. for t oza maximum, c l = 25 pf to 185 mhz or 10 pf to 200 mhz 21. these figures are for illustration purposes only. the actual ate loads may vary. [+] feedback
preliminary roboclock ? CY7B9945V document number: 38-07336 rev. *j page 11 of 15 ordering code definitions ordering information propagation delay (ps) max. speed (mhz) ordering code package name package type operating range pb-free 250 200 CY7B9945V-2axc az52 52-pin tqfp commercial 200 CY7B9945V-2axct az52 52-pin tqfp ? tape and reel commercial 250 200 CY7B9945V-2axi az5 2 52-pin tqfp industrial 200 CY7B9945V-2axit az52 52-pin tq fp ? tape and reel industrial cy xxxxxx v 2 -a x pb-free, blank = leaded 52-pin tqfp package speed grade operating voltage: 3.3 v part identifier company code: cy = cypress c temperature range: c = commercial t t = tape and reel, blank = tube [+] feedback
preliminary roboclock ? CY7B9945V document number: 38-07336 rev. *j page 12 of 15 package diagram figure 6. 52-pin thin plastic quad flat pack (10 10 1.4 mm) a52 and az52 51-85131 *a [+] feedback
preliminary roboclock ? CY7B9945V document number: 38-07336 rev. *j page 13 of 15 acronyms document conventions units of measure table 6. acronyms used in this documnent acronym description fsm finite state machine lvpecl low-voltage positive emitter coupled logic lvttl low-voltage transistor transistor logic oe output enable rms root mean square pll phase locked loop tqfp thin quad flat pack vco voltage controlled oscillator table 7. units of measure symbol unit of measure symbol unit of measure c degrees celsius vrms microvolts root-mean-square db decibels w microwatts dbc/hz decibels relative to the carrier per hertz ma milliamperes fc femtocoulomb mm millimeters ff femtofarads ms milliseconds hz hertz mv millivolts kb 1024 bytes na nanoamperes kbit 1024 bits ns nanoseconds khz kilohertz nv nanovolts k kilohms ohms mhz megahertz pa picoamperes m megaohms pf picofarads a microamperes pp peak-to-peak f microfarads ppm parts per million h microhenrys ps picoseconds s microseconds sps samples per second v microvolts sigma: one standard deviation [+] feedback
preliminary roboclock ? CY7B9945V document number: 38-07336 rev. *j page 14 of 15 document history page document title: CY7B9945V roboclock ? high speed multi-phase pll clock buffer document number: 38-07336 revision ecn orig. of change submission date description of change ** 111747 ctk 03/04/02 new data sheet *a 116572 hwt 09/05/02 added ttb features *b 119078 hwt 10/16/02 corrected the following items in the electrical characteristics table: i iil ,i iih ,i iim specifications from: three level input pins excluding fbfo to fs[0:2],if[0:3],fbds[0:1] and fbfo to 2f[0:1],[1 :2]ds[0:1],fbfo common mode range (v com ) from v cc to v cc ?0.2 corrected typo tqfp to lqfp in features *c 124645 rgl 03/20/03 corrected typo lqfp to tqfp in features *d 128464 rgl 07/25/03 added clock input frequency (f in ) specifications in the switching characteristics table. *e 272075 rgl see ecn minor change: fixed the typical outputs (fig. 1) diagram *f 1187144 kvm see ecn updated ordering informatio n table, primarily to add pb-free devices *g 2761988 cxq 09/10/09 changed instances of ?50w? to ?50 ? on page 1. changed ?pb? to ?lead? in ordering information package type section. added ?not recommended for new designs? note to all pb packages. *h 2891379 kvm 03/12/2010 added table of contents updated ordering information table updated package diagram updated sales, solutions, and legal information *i 2905846 kvm 04/06/2010 removed inactive part from ordering information table. *j 3196237 bash 03/15/11 template updates. included ordering code definitions, acronyms, and units of measure. [+] feedback
document number: 38-07336 rev. *j revised march 15, 2011 page 15 of 15 psoc designer?, programmable system-on-chip ?, and psoc express? are trademarks and psoc? is a registered trademark of cypress s emiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations.purchase of i 2 c components from cypress or one of its sublicense d associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.all products and company names mentioned in this document may be the trademarks of their respective holders. roboclock is a registered trademark, and total ti ming budget and ttb are trademarks of cypress semiconductor. preliminary roboclock ? CY7B9945V ? cypress semiconductor corporation, 2002-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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